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128-Bit
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While there are currently no mainstream general-purpose processors built to operate on 128-bit integers or 128-bit addresses, a number of processors do have specialized ways to operate on 128-bit chunks of data.
Representation
128-bit processors could be used for addressing directly up to 2128 (over 3.40×1038 bytes, which would greatly exceed the total data captured, created, or replicated on Earth as of 2018, which has been estimated to be around 33 zettabytes (over 274 bytes).((The Digitalization of the World from Edge to Core, https://seagate.com/files/www-content/our-story/trends/files/idc-seagate-dataage-whitepaper.pdf, Seagate Technology, Publisher: International Data Corporation IDC, https://web.archive.org/web/20210907102915/https://www.seagate.com/files/www-content/our-story/trends/files/idc-seagate-dataage-whitepaper.pdf))
A 128-bit register can store 2128 (over 3.40 × 1038) different values. The range of integer values that can be stored in 128 bits depends on the integer (computer science)#Value and representation|integer representation used. With the two most common representations, the range is 0 through 340,{{Zwsp}}282,{{Zwsp}}366,{{Zwsp}}920,{{Zwsp}}938,{{Zwsp}}463,{{Zwsp}}463,{{Zwsp}}374,{{Zwsp}}607,{{Zwsp}}431,{{Zwsp}}768,{{Zwsp}}211,{{Zwsp}}455 (2128 − 1) for representation as an (signedness|unsigned) binary number, and −170,{{Zwsp}}141,{{Zwsp}}183,{{Zwsp}}460,{{Zwsp}}469,{{Zwsp}}231,{{Zwsp}}731,{{Zwsp}}687,{{Zwsp}}303,{{Zwsp}}715,{{Zwsp}}884,{{Zwsp}}105,{{Zwsp}}728 (−2127) through 170,{{Zwsp}}141,{{Zwsp}}183,{{Zwsp}}460,{{Zwsp}}469,{{Zwsp}}231,{{Zwsp}}731,{{Zwsp}}687,{{Zwsp}}303,{{Zwsp}}715,{{Zwsp}}884,{{Zwsp}}105,{{Zwsp}}727 (2127 − 1) for representation as two's complement.
Quadruple-precision floating-point format|Quadruple precision (128-bit) floating-point arithmetic|floating-point numbers can store 113-bit fixed-point arithmetic|fixed-point numbers or integer (computer science)|integers accurately without losing significant figures|precision (thus 64-bit integers in particular). Quadruple precision floats can also represent any position in the observable universe with at least micrometer precision.{{Citation needed|date=May 2020}}
Decimal128 floating-point numbers can represent numbers with up to 34 significant digits.
History
A 128-bit multicomparator was described by researchers in 1976.[{{cite journal|last1=Mead|first1=Carver A.|author-link=Carver Mead|last2=Pashley|first2=Richard D.|last3=Britton|first3=Lee D.|last4=Daimon|first4=Yoshiaki T.|last5=Sando|first5=Stewart F., Jr.|date=October 1976|title=128-Bit Multicomparator|url=https://authors.library.caltech.edu/53685/1/01050799.pdf|url-status=live|journal=IEEE Journal of Solid-State Circuits|volume=11|issue=5|pages=692–695|doi=10.1109/JSSC.1976.1050799|bibcode=1976IJSSC..11..692M|s2cid=27262034|archive-url=https://web.archive.org/web/20181103205511/https://authors.library.caltech.edu/53685/1/01050799.pdf|archive-date=3 November 2018}}]
The IBM System/360 Model 85,[{{cite journal|doi=10.1147/sj.71.0022|volume=7 | title=Structural aspects of the System/360 Model 85, III: Extensions to floating-point architecture|year=1968|journal=IBM Systems Journal|pages=22–29|author=Padegs A}}] and IBM System/370 and its successors, support 128-bit floating-point arithmetic.
The Siemens 7.700 and 7.500 series mainframes and their successors support 128-bit floating-point arithmetic.[{{cite manual|title=Assembler Instructions (BS2000/OSD)|number=U3119-J-Z125-2-7600|year=1993|url=https://bs2manuals.ts.fujitsu.com/download/manual/959.1}}]
Most modern CPUs feature single instruction, multiple data (SIMD) instruction sets (Streaming SIMD Extensions, AltiVec etc.) where 128-bit vector registers are used to store several smaller numbers, such as four 32-bit floating-point numbers. A single instruction can then operate on all these values in parallel. However, these processors do not operate on individual numbers that are 128 binary digits in length; only their vector registers have the size of 128 bits.
The DEC VAX supported operations on 128-bit integer ('O' or octaword) and 128-bit floating-point ('H-float' or HFLOAT) datatypes. Support for such operations was an upgrade option rather than being a standard feature. Since the VAX's registers were 32 bits wide, a 128-bit operation used four consecutive registers or four longwords in memory.
The ICL 2900 Series provided a 128-bit accumulator, and its instruction set included 128-bit floating-point and packed decimal arithmetic.
A CPU with 128-bit multimedia extensions was designed by researchers in 1999.[{{Cite journal|last1=Suzuoki|first1=M.|last2=Kutaragi|first2=K.|last3=Hiroi|first3=T.|last4=Magoshi|first4=H.|last5=Okamoto|first5=S.|last6=Oka|first6=M.|last7=Ohba|first7=A.|last8=Yamamoto|first8=Y.|last9=Furuhashi|first9=M.|date=November 1999|title=A microprocessor with a 128-bit CPU, ten floating-point MAC's, four floating-point dividers, and an MPEG-2 decoder|journal=IEEE Journal of Solid-State Circuits|volume=34|issue=11|pages=1608–1618|doi=10.1109/4.799870|last10=Tanaka|first10=M.|last11=Yutaka|first11=T.|last12=Okada|first12=T.|last13=Nagamatsu|first13=M.|last14=Urakawa|first14=Y.|last15=Funyu|first15=M.|last16=Kunimatsu|first16=A.|last17=Goto|first17=H.|last18=Hashimoto|first18=K.|last19=Ide|first19=N.|last20=Murakami|first20=H.|last21=Ohtaguro|first21=Y.|last22=Aono|first22=A.|bibcode=1999IJSSC..34.1608S}}]
The Dreamcast and the PlayStation 2 among the Sixth generation of video game consoles used the term "128-bit" in their marketing to describe their capability. The Playstation 2's CPU had 128-bit Single instruction, multiple data|SIMD capabilities.[John L. Hennessy and David Patterson (scientist)|David A. Patterson. "Computer Architecture: A Quantitative Approach, Third Edition". {{ISBN|1-55860-724-2}}][Keith Diefendorff. "Sony's Emotionally Charged Chip". Microprocessor Report, Volume 13, Number 5, April 19, 1999. Microdesign Resources.] Neither console supported 128-bit addressing or 128-bit integer arithmetic.
Hardware
The RISC-V ISA specification from 2016 includes a reservation for a 128-bit version of the architecture, but the details remain undefined intentionally, because there is yet so little practical experience with such large memory systems.[{{cite web|last1=Waterman|first1=Andrew|last2=Asanović|first2=Krste|author-link2=Krste Asanović|title=The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA version 2.2|id=EECS-2016-118|url=https://riscv.org/technical/specifications/|publisher=University of California, Berkeley|access-date=25 May 2017}}]
Graphics processing unit (GPU) chips commonly move data across a 128-bit bus.[{{cite web|url=https://www.tomshardware.com/reviews/graphics-beginners,1288-8.html|title=The Graphics Processor|last=Woligroski|first=Don|date=24 July 2006|website=Tom's Hardware|archive-url=https://archive.today/20130411235050/http://www.tomshardware.com/reviews/graphics-beginners,1288-8.html|archive-date=11 April 2013|url-status=live|access-date=24 February 2013}}]
Software
In the same way that compilers emulate e.g. 64-bit integer arithmetic on architectures with register sizes less than 64 bits, some compilers also support 128-bit integer arithmetic. For example, the GNU Compiler Collection|GCC C compiler 4.6 and later has a 128-bit integer type __int128 for some architectures.[{{cite web|title=GCC 4.6 Release Series - Changes, New Features, and Fixes|url=https://gcc.gnu.org/gcc-4.6/changes.html|access-date=25 July 2016}}] GCC and compatible compilers signal the presence of 128-bit arithmetic when the macro __SIZEOF_INT128__ is defined.[{{cite web | title = 128-bit integer - nonsensical documentation? | author = Marc Glisse | date = August 26, 2015 | publisher = GCC-Help |url = https://gcc.gnu.org/ml/gcc-help/2015-08/msg00185.html | access-date = January 23, 2020 }}] For the C programming language, 128-bit support is optional, e.g. via the int128_t type, or it can be implemented by a compiler-specific extension. The Rust (programming language)|Rust programming language has built-in support for 128-bit integers (originally via LLVM), which is implemented on all platforms.[{{Cite web|title=i128 - Rust|url=https://doc.rust-lang.org/std/primitive.i128.html|access-date=2020-06-25|website=doc.rust-lang.org}}] A 128-bit type provided by a C compiler can be available in Perl via the Math::Int128 module.[{{Cite web |title=Math::Int128 |url=https://metacpan.org/pod/Math::Int128 |website=metacpan.org |access-date=2020-06-25}}]
=Uses
=
* The free software used to implement RISC-V CPU architecture|architecture is defined for 32, 64 and 128 bits of integer data width.
* Universally unique identifiers (UUID) consist of a 128-bit value.
* IPv6 routes computer network traffic amongst a 128-bit range of addresses.
* ZFS is a 128-bit file system.
* 128 bits is a common key size for symmetric ciphers and a common block size for block ciphers in cryptography.
* The IBM i virtual instruction set defines all pointers as 128-bit. This gets translated to the hardware's real instruction set as required, allowing the underlying hardware to change without needing to recompile the software. Past hardware was 48-bit Complex instruction set computer|CISC, while current hardware is 64-bit PowerPC. Because pointers are defined to be 128-bit, future hardware may be 128-bit without software incompatibility.
* Increasing the word size can speed up Arbitrary-precision arithmetic|multiple precision mathematical libraries, with applications to cryptography, and potentially speed up algorithms used in complex mathematical processing (numerical analysis, signal processing, complex photo manipulation|photo editing and audio signal processing|audio and video processing).
* MD5 is a hash function producing a 128-bit hash value.
* Apache Avro uses a 128-bit random number as synchronization marker for efficient splitting of data files.[{{Cite web|url=https://mail-archives.apache.org/mod_mbox/avro-user/201301.mbox/%3CCAHNLEqvRrdA3qhGmDs8jCXGP-TeK24DTmZ1sfDgfu10mW=PB0Q@mail.gmail.com%3E|title=Re: Synchronization Markers|last=Kleppmann|first=Martin|date=24 January 2013|archive-url=https://web.archive.org/web/20150927205705/https://mail-archives.apache.org/mod_mbox/avro-user/201301.mbox/%3CCAHNLEqvRrdA3qhGmDs8jCXGP-TeK24DTmZ1sfDgfu10mW=PB0Q@mail.gmail.com%3E|archive-date=27 September 2015|url-status=live}}][{{Cite web|url=https://avro.apache.org/docs/1.8.0/spec.html#Object+Container+Files|title=Apache Avro 1.8.0 Specification|publisher=Apache Software Foundation}}]
Research It More
Research:
* ddg>128-bit on DuckDuckGo
* oreilly>128-bit on O'Reilly
* toms>128-bit on TomsHardware.com
* github>128-bit on GitHub
* ms>128-bit on Microsoft.com
* ibm>128-bit on IBM.com
* python>128-bit on Python.org
* java>128-bit on docs.oracle.com
* redhat>128-bit on developers.redhat.com
* mdn>128-bit on developer.mozilla.org
* reddit>128-bit on Reddit
* stackoverflow>128-bit on StackOverflow
* stackexchange>128-bit on StackExchange.com
* superuser>128-bit on SuperUser.com
* serverfault>128-bit on ServerFault.com
* macworld>128-bit on MacWorld.com
* pcworld>128-bit on PCWorld.com
* networkworld>128-bit on NetworkWorld.com
* infoworld>128-bit on InfoWorld.com
* scholar>128-bit on scholar.google.com
* youtube>128-bit on YouTube
Fair Use Sources
Fair Use Sources:
* ddg>128-bit on DuckDuckGo
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